What if SMIC reaches TSMC-class 5nm economics without EUV?
SMIC hitting TSMC-class 5nm economics neutralizes the EUV moat — but the cascade is bullish (de-escalation): trade_tension negative, semis and Nasdaq rally, yuan and China internet up as the chip cold war thaws. The de-escalation analogue is the 2019 Phase-One trade-truce relief rally. Transmission: erasing China's cost penalty reduces the strategic urgency of export controls, easing the whole complex. Skeptic's note: roots correctly carry negative trade_tension/semiconductor_risk — this is the rare risk-on AI scenario.
Every number ships with its receipt — the odds, the range, the precedents, and a public grade at Reality Check. The statistical machinery that produces it is proprietary.
The butterfly cascade
How this trigger trickles across markets, left → right — the root shock, its first‑order moves, then the ripple effects. Drag any node; tap a market for its real price history.
Resolution timeline — how this probability is moving
Our model's odds (electric blue) over time vs the market's (Polymarket, amber), from the past toward the 1–3 years horizon. Each dot is a real macro event that nudged the probability — green pushed it up, red pushed it down. Tap a dot for the source. Loading the probability audit trail…
What it would mean
If this plays out, it is a mixed shock. SMIC lifts DUV 5nm yields near TSMC parity, erasing the cost penalty and neutralizing the EUV export-control moat. The trigger decomposes into signed root‑shocks — China growth ▲ · Semiconductor supply risk ▼ · Trade tension ▼ — which propagate through our causal graph to the markets below.